1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to a semiconductor memory device allowing selection of the number of sense amplifiers to be activated simultaneously. The invention has particular applicability to dynamic random access memories.
2. Description of the Background Art
In recent years, semiconductor memories such as dynamic random access memories (will be called as "DRAMs") and static random access memories (will be called as "SRAMs") have been used in various electronic equipments and have been integrated to a higher degree in accordance with the advance of manufacturing technology. Although the high integration of the semiconductor memories has brought about various advantages for reducing sizes and improving performance of electronic equipments, it also increases a possibility of error in data reading operations of the highly integrated semiconductor memory devices.
FIG. 1 is a block diagram of a DRAM, which shows the background of the invention (and also shows an embodiment of the invention, as will be described later). Referring to FIG. 1, the DRAM includes a memory cell array 1, a row decoder 2 for decoding row address signals RA0-RAi, a column decoder 3 for decoding column address signals CA0-CAi, a sense amplifier 15, and an IO gate 16. A row address buffer 13 receives row address signals RA0-RAi included in externally applied address signals A0-Ai, and applies the same to row decoder 2. A column address buffer 14 receives column address signals CA0-CAi included in address signals A0-Ai, and applies the same to column decoder 3 and address transition detecting (will be called as "ATD") circuit 9. Line 100 indicates a semiconductor substrate.
The DRAM further comprises a timing signal generator 17 which is responsive to a row address strobe signal /RAS and a column address strobe signal /CAS to generate various internal timing signals. Timing signal generator 17 is responsive to state control signals /RAS and /CAS to generate the timing signals required for controlling the DRAM shown in FIG. 1. A WE buffer 22 receives an externally applied write enable signal /WE. An OE buffer 23 receives an externally applied output enable signal /OE.
Input data DI to be written is applied through an input buffer 19 to a write buffer 18. Write buffer 18 applies the input data signal to memory cell array 1 through an IO line 24 and IO gate 16. In memory cell array 1, the input data signal is written in memory cells (not shown) selected by row decoder 2 and column decoder 3. In a reading operation, the data signal read from the memory cells designated by row decoder 2 and column decoder 3 is applied through IO gate 16 and IO line 24 to a preamplifier 20. The read data signal amplified by preamplifier 20 is further amplified by a main amplifier 21, and then is externally supplied as an output data DO.
The DRAM shown in FIG. 1 further includes a row pre-decoder 5, a sense amplifier activating circuit 6, a column interlock releasing circuit 7, a sense amplifier enabling circuit 8, an ATD circuit 9, a column decoder enabling circuit 10, a bonding option circuit 11, and a mode control circuit 12. These circuits will be described below in detail.
FIG. 8 is a circuit diagram of bonding option circuit 11 shown in FIG. 1. Referring to FIG. 8, bonding option circuit 11 includes a bonding pad 111 formed on semiconductor substrate 100, a high resistor 112, and cascade-coupled inverters 113 and 114. Bonding pad 111 is selectively connected to an input pin (or input lead) 110 by gold wire 115. Input pin 110 is grounded.
When bonding pad 111 is connected through gold wire 115 to grounded input pin 110, bonding option circuit 11 supplies a mode selecting signal /.o slashed..sub.A at a low level. When bonding pad 111 is not connected to input pin 110, bonding option circuit 11 supplies signal /.o slashed..sub.A at a high level. Mode selecting signal /.o slashed..sub.A is applied to mode control circuit 12 shown in FIG. 1. Mode control circuit 12 is responsive to signal /.o slashed..sub.A to perform the following control in the DRAM.
FIG. 9 is a schematic diagram showing sizes of memory cell array 1 which is simultaneously accessed in the DRAM shown in FIG. 1. A memory block MB1 shown in FIG. 9(A) has the size of 1024 bits in the X direction and 256 bits in the Y direction. Thus, 256 sense amplifiers (not shown) provided in memory block MB1 are simultaneously activated in one reading operation or one refresh. A memory block MB2 shown in FIG. 9(B) has the size of 512 bits in the X direction and 512 bits in the Y direction. Thus, 512 sense amplifiers (not shown) provided in memory block MB2 are simultaneously activated in one reading operation or one refresh.
The DRAM shown in FIG. 1 is responsive to a mode selection signal /.o slashed..sub.A supplied from bonding option circuit 11 to equivalently realize the DRAM of the type shown in either FIG. 9(A) or FIG. 9(B). Thus, the DRAM shown in FIG. 1 is responsive to signal /.o slashed..sub.A at the high level to form the DRAM shown in FIG. 9(A) (1/8 divisional operation), and is also responsive to signal /.o slashed..sub.A at the low level to form the DRAM shown in FIG. 9(B) (1/4 divisional operation).
FIGS. 10 and 11 are circuit diagrams showing a front half 5a and a rear half 5b of row pre-decoder 5 shown in FIG. 1, respectively. Row pre-decoder 5 shown in FIG. 1 is formed of front half circuit 5a and rear half circuit 5b. Circuits 5a and 5b decode externally applied higher row address signals RAi, RAi-1 and RAi-2 to supply pre-decode signals AX0-AX7. Row address signal RAi indicates the most significant row address signal. When mode selecting signal /.o slashed..sub.A is at the low level, the most significant row address signal RAi is ignored. More specifically, when signal /.o slashed..sub.A is at the low level, pre-decode signals AX0-AX7 are not affected by the most significant row address signal RAi. Pre-decode signals AX0-AX7 are supplied to sense amplifier activating circuit 6 shown in FIG. 1.
FIG. 12 is a block diagram showing the 1/8 divisional operation of the DRAM shown in FIG. 1. Although memory cell array 1 is shown as one block in FIG. 1, memory cell array 1 is practically divided into, e.g., four memory blocks MBa, MBb, MBc and MBd, as shown in FIG. 12. Row decoder 2 is also divided into row decoders 2a, 2b, 2c and 2d which are provided for the memory blocks, respectively. Column decoder 3 is divided into column decoders 3a and 3b.
Regions AX0-AX7 shown in each memory block are accessed by corresponding pre-decode signals AX0-AX7, respectively. For example, when pre-decode signal AX1 is at the high level, a total of eight regions (hatched regions in the figure) in memory blocks MBa-MBd are accessed.
The block diagram of FIG. 12 shows the 1/8 divisional operation, i.e., the operation performed when mode selecting signal /.o slashed..sub.A is at the high level. In the 1/8 divisional operation, eight regions in total are simultaneously accessed, so that memory block MB1 shown in FIG. 9(A) is equivalently realized.
FIG. 13 is a block diagram for showing the 1/4 divisional operation of the DRAM shown in FIG. 1. When the 1/4 divisional operation is selected, bonding option circuit 11 shown in FIG. 1 supplies mode selecting signal /.o slashed..sub.A at the low level. Therefore, circuits 5a and 5b shown in FIGS. 10 and 11 supply pre-decode signals AX1 and AX5 at the high level. Consequently, as shown in FIG. 13, totally eight regions in total (hatched regions in the figure) in memory blocks MBa-MBd are simultaneously accessed. This means that the DRAM of the type shown in FIG. 9(B) is equivalently realized in the 1/4 divisional operation.
FIG. 14 is a circuit block diagram showing, as an example, memory block MBc and its peripheral circuit shown in FIG. 12. Referring to FIG. 14, memory block MBc shown in FIG. 12 includes a total of sixteen regions MBc0-MBc15. Regions MBc0 and MBc1 are accessed in response to pre-decode signal AX0 at the high level. Similarly, regions MBc14 and MBc15 are accessed in response to pre-decode signal AX7 at the high level. Each region, e.g., region MBc0 comprises n sense amplifiers SA1-SAn connected to n bit line pairs, as shown in FIG. 14.
Sense amplifier enabling circuit 6 comprises a total of sixteen activation signal generating circuits (ASG) 60-75. For example, activation signal generating circuits 60 and 61 supply activation signals S.sub.N and S.sub.P in response to pre-decode signal AX0. All sense amplifiers SA1-SAn provided in region MBc0 are simultaneously activated in response to signals S.sub.N and S.sub.P supplied from activation signal generating circuit 60.
Column decoder 3b includes column selecting signal generating circuits CD1-CDn which generate column selecting signals Y1-Yn, respectively. Column selecting signal generating circuits CD1-CDn are enabled in response to an enable signal .o slashed..sub.Y supplied from column decoder enabling circuit 10 shown in FIG. 1. Row decoder 2c comprises a total of sixteen word line drive circuits RD0-RD15. It is noted that the other memory blocks shown in FIG. 12 have the circuit constructions similar to that of the circuit shown in FIG. 14.
FIG. 15 is a circuit diagram of one memory cell column in the memory block. Referring to FIG. 15, memory cell MC is connected to one bit line BL1 forming the bit line pair. Memory cell MC includes a switching transistor Qs and a capacitor Cs holding signal charges. Transistor Qs is turned on in response to a word line signal WL. Bit line pair BL1 and/BL1 is connected to IO line pair IO and /IO through NMOS transistors Q8 and Q9 forming a Y-gate circuit. Transistors Q8 and Q9 operate in response to column selecting signal Y1.
Sense amplifier SA1, which is provided for amplifying a small or slight potential difference between bit lines BL1 and/BL1, includes NMOS transistors Q1 and Q2 and PMOS transistors Q3 and Q4. Sense amplifier SA1 is activated in response to activation signals S.sub.N and S.sub.P. Specifically, there are provided transistors Q.sub.SN and Q.sub.SP for the activation, which are turned on in response to signals S.sub.N and S.sub.P.
In the reading operation, word line signal WL rises after the equalization of bit line pair BL1 and /BL1. Since transistor Qs is turned on, a small potential difference appears between bit lines BL1 and /BL1 in accordance with the signal charge stored in memory cell MC. Sense amplifier SA1 is activated in response to activation signals S.sub.N and S.sub.P to amplify the slight potential difference between bit lines BL1 and/BL1. After the amplification by sense amplifier SA1, transistors Q8 and Q9 are turned on by column selecting signal Y1 at the high level applied thereto, so that the amplified data signal is transmitted to IO line pair I0 and /IO. The data signal transmitted to IO line pair is amplified by preamplifier 20 and main amplifier 21 shown in FIG. 1, and then is externally supplied as output data DO.
FIG. 16 is a circuit diagram of column interlock releasing circuit 7 and sense amplifier enabling circuit 8 shown in FIG. 1. Referring to FIG. 16, circuit 8a is responsive to externally applied signal /RAS to generate signals .o slashed..sub.NF, .o slashed..sub.N and .o slashed..sub.P. Circuit 7a is responsive to signals .o slashed..sub.N and /RAS to supply a column interlock releasing signal /.o slashed..
FIG. 17 is a circuit diagram of one activation signal generating circuit (ASG) 60 shown in FIG. 14. Activation signal generating circuit 60 is responsive to pre-decode signal AX0 and signals .o slashed..sub.P, .o slashed..sub.N and .o slashed..sub.NF to generate sense amplifier activation signals S.sub.P and S.sub.N. Generated signals S.sub.P and S.sub.N are applied to gates of transistors Q.sub.SP and Q.sub.SN shown in FIG. 15, respectively.
FIGS. 18 and 19 are circuit diagrams of front and rear halves of ATD circuit 9 shown in FIG. 1. Front half circuit 9a shown in FIG. 18 is responsive to the transition of column address signal CAi to generate a pulse signal CATi. Rear half circuit 9b shown in FIG. 19 is responsive to column interlock releasing signal /.o slashed. and signal CATi to generate a pulse ATD, which is applied to column decoder enabling circuit 10 shown in FIG. 1.
FIG. 20 is a circuit diagram of column decoder enabling circuit 10 shown in FIG. 1. Referring to FIG. 20, column decoder enabling circuit 10 is responsive to pulse ATD and column interlock releasing signal /.o slashed. to generate column decoder enable signal .o slashed..sub.Y.
As already stated, DRAM shown in FIG. 1 can selectively operate in the types or operation modes shown in either FIG. 9(A) or FIG. 9(B) by using the bonding option circuit. The constructions in FIG. 9(A) and FIG. 9(B) differ from each other in the number of the sense amplifiers to be activated simultaneously. Specifically, when the DRAM operates in the operation mode shown in FIG. 9(B), the number of the sense amplifiers to be activated simultaneously is double the number in the operation mode shown in FIG. 9(A).
Generally, as the number of the sense amplifiers to be activated simultaneously increases, a peak value of the current consumed in a short activating period increases. Therefore, power supply potential VDD decreases in this short period, and thus amplifying capability of the sense amplifier decreases. As a result, transistors Q8 and Q9 are turned on before, e.g., sense amplifier SA1 shown in FIG. 15 sufficiently amplifies the slight potential difference between bit lines BL1 and /BL1, so that, in some cases, the data signal on bit line pair BL1 and /BL1 may be inverted due to the signal charges remaining on the IO line pair. This means that error is caused in the data reading operation.
When the DRAM operates in the operation mode shown in FIG. 9(B), larger number of sense amplifiers are simultaneously activated, so that the possibility of error in the data reading operation increases, as compared with the case shown in FIG. 9(A).